1. Field of the Invention:
The present invention relates to a scanning pulse generating circuit composed mainly of MOS transistors and suitable for use in, for example, solid-state imaging devices.
2. Description of the Related Art:
FIG. 1A shows a known scanning pulse generating circuit which drives pixels of a solid-state imaging device. This circuit has a plurality of basic circuits each composed of a two-stage inverter comprising a first-stage inverter composed of MOS transistors Q.sub.12 and Q.sub.13 and a second-stage inverter composed of MOS transistors Q.sub.15 and Q.sub.16, and a pair of signal transmitting MOS transistors Q.sub.11 and Q.sub.14. The basic circuits 11.sub.-1, 11.sub.-2, 11.sub.-3, . . . are connected in a cascade manner and output terminals 12.sub.-1, 12.sub.-2, 12.sub.-3, . . . are led from the connections between adjacent stages of the cascade.
In operation, a start pulse ST (see FIG. 1B) is input to the signal transmitting transistor Q.sub.11. At the same time, clock pulses .phi..sub.11 and .phi..sub.12 are input to the signal transmitting transistors Q.sub.11 and Q.sub.14. The start pulse ST is delayed by a time corresponding to the period of the clock pulse .phi..sub.12 so that output pulses V.sub.01, V.sub.02, V.sub.03, . . . are derived from the output terminals 12.sub.-1, 12.sub.-2, 12.sub.-3, . . . of the basic circuits 11.sub.-1, 11.sub.-2, 11.sub.-3, . . . of the respective stages, as shown in FIG. 1B.
Each of the MOS transistors used in the scanning pulse generating circuit of FIG. 1A is of the N-channel type. A symbol V.sub.DD repesents positive D.C. source voltage, while V.sub.SS represents grounding voltage. Symbols V.sub.11, V.sub.12 and V.sub.13 appearing in FIG. 1B represent the input voltage waveform of the first-stage inverter circuit, output voltage waveform of the first-stage inverter circuit and the input voltage waveform of the second-stage inverter circuit.
This known scanning pulse generating circuit is advantageous in that the operational margin of the scanning pulse generating circuit is high and in that the wiring interconnecting the circuit elements is suitable for attaining a higher density of the circuit arrangement. Unfortunately, however, this known scanning pulse generating circuit suffers from the following disadvantages.
(1) The voltage of the "H" level of the output signal from the basic circuit of each stage is affected by a fluctuation in the threshold voltage of the load transistor Q.sub.16 incorporated in the second-stage inverter of the basic circuit of the same stage, so that the basic circuits of different stages provide different levels of output signal. PA0 (2) The voltage of the "H" level of the output signal is considerably lowered from the level of the D.C. source voltage V.sub.DD. PA0 (3) Either one of the two stages of inverter is operative to conduct the inverting operation in all the basic circuits so that electric current is continuously supplied to all basic circuits, whereby the power consumption is increased. This poses a serious problem particularly when a multiplicity of stages of basic circuit, e.g., several hundreds of stages, are employed as in the case of the scanning circuit for a solid-state imaging device.
Using Complementary MOS transistors (referred to as CMOS hereinafter), a scanning pulse generating circuit is obtainable which is capable of operating at high speed with reduced power consumption and which can produce an "H" output level which is substantially the same as the source voltage, i.e., without a substantial drop in the voltage supplied from the source.
However, production of a scanning pulse generating circuit using CMOS transistors arranged in the form of an integrated circuit inconveniently requires a specific production process for forming CMOS transistors and the production process is inevitably complicated. Preferably, the scanning pulse generating circuit is constituted solely by N-channel MOS transistors or P-channel MOS transistros depending on whether the outputs to be obtained are of positive or negative voltage.